1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and an abnormal oscillation detection method for the semiconductor integrated circuit. In particular, the present invention relates to a clock monitor technique of a semiconductor integrated circuit with plural clocks.
2. Description of Related Art
In recent years, there is advanced speed-up of a semiconductor integrated circuit along with making to a highly-functionalization and a highly performance of a system. For it achieves a speed-up of the semiconductor integrated circuit at low power consumption and low price, an oscillator is a conventional composition. For example, a semiconductor integrated circuit according to Japanese Unexamined Patent Application Publication No. 2006-172202 equips with a PLL (Phase Locked Loop) multiplying a clock of the oscillator, and uses a clock of the PLL as an operation clock of a microcomputer.
FIG. 5 is a block diagram showing a semiconductor integrated circuit according to Japanese Unexamined Patent Application Publication No. 2006-172202. The semiconductor integrated circuit 100 includes an oscillator 201, a PLL 301, an abnormal oscillation detection unit 401, a flash ROM (Read Only Memory) 501, a CPU (Central Processing Unit) 601, and plural peripheral devices (701-1-701-n: n is a natural number). The abnormal oscillation detection unit 401 includes an internal reset signal generation circuit 801 (reset generator), and a clock monitor 901. The internal reset signal generation circuit 801 includes a signal generation unit 104.
The oscillator 201 receives a first oscillator output signal supplied from a first oscillator input terminal 101 and a second oscillator input signal supplied from a second oscillator input terminal 102, and outputs a clock signal 21 (an oscillator output signal). The oscillator output signal 21 output from the oscillator 201 is supplied to each the PLL 301 and the clock monitor 901. The PLL 301 receives the oscillator output signal 21, generates a PLL output signal 231, and outputs the PLL output signal 231 to the CPU 601. The clock monitor 901 generates an abnormal oscillation detection signal 241 based on the oscillator output signal 21 and a clock (ring oscillator output signal) 221 supplied from the flash ROM 501, and outputs the abnormal oscillation detection signal 241 to the internal reset signal generation circuit 801. The internal reset signal generation circuit 801 generates an internal reset signal 251 based on a reset signal 271 supplied from a terminal reset signal input terminal 103 and the abnormal oscillation detection signal 241 supplied from the clock monitor 901 and outputs the internal reset signal 251 to the CPU 601.
Therefore, when it occurs an abnormal oscillation of the oscillator output signal 21 supplied from the oscillator 201, it can stop appropriately an operation of the semiconductor integrated circuit 100, corresponding the abnormality. In this case, the semiconductor integrated circuit 100 measures a clock frequency of the oscillator output signal 21 with the ring oscillator output signal 221 supplied from the flash ROM 501, at the clock monitor 901. The semiconductor integrated circuit 100 monitors the operation of the oscillator 201 by comparing the measured clock frequency with a comparison value provided beforehand. The comparison value indicates a frequency of a predetermined range (guaranteed operating range). For example, when the semiconductor integrated circuit 100 is designed to operate in corresponding the oscillator output signal 21 of a range of 5 MHz to 7 MHz, the abnormal oscillation detection unit 401 generates the abnormal oscillation detection signal 241 when it detects a frequency (for examples, a frequency of 8 MHz) out of the comparison value. Therefore, when a signal including a high-frequency content (for example, the above-mentioned frequency content of 8 MHz) exceeded a clock frequency at normal times is output from the oscillator 201, the semiconductor integrated circuit 100 determines that the high-frequency content is an abnormal oscillation, and stops operations of the CPU 601 and the peripheral device (701-1-701-n).
Further, a semiconductor integrated circuit according to Japanese Unexamined Patent Application Publication No. 2002-41178 divides a PLL output signal with a frequency divider, and determines whether it occurs an abnormal oscillation in PLL output signal with a divider clock frequency and input clock.